Unit name | VLSI Design 3 |
---|---|
Unit code | EENG34050 |
Credit points | 10 |
Level of study | H/6 |
Teaching block(s) |
Teaching Block 2 (weeks 13 - 24) |
Unit director | Professor. Dinesh Pamunuwa |
Open unit status | Not open |
Pre-requisites | |
Co-requisites |
None |
School/department | School of Electrical, Electronic and Mechanical Engineering |
Faculty | Faculty of Engineering |
This unit introduces students to the principles of digital chip design.
Starting from a functional model of a MOSFET, analysis and design considerations for transistor level implementations of basic logic gates for different digital logic families are covered. These include static and dynamic logic styles for both combinational and sequential circuits.
Principles of synchronous system design are covered in detail, as are design techniques for dealing with signal integrity issues, and high performance and low power requirements.
The students will make extensive use of industry standard CAD tools for integrated circuit design, simulation and layout and gain experience in the design process from schematic entry to final tape-out of the chip.
Having completed this unit, students will be able to:• Analyse digital logic circuits for functionality, performance, energy and power consumption
Lectures and laboratory sessions
Two take-home quizzes, 10% (ILOs 1-3, 5-6)
Design exercises using Cadence in the laboratory, plus analysis tasks, 30% (ILOs 1-4)
Exam on lecture material, 2 hours, 60% (ILOs 1-3, 5-6)