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Unit information: Digital Design, Group Project in 2018/19

Please note: It is possible that the information shown for future academic years may change due to developments in the relevant academic field. Optional unit availability varies depending on both staffing and student choice.

Unit name Digital Design, Group Project
Unit code EENG28010
Credit points 10
Level of study I/5
Teaching block(s) Teaching Block 2 (weeks 13 - 24)
Unit director Dr. Dinesh Pamunuwa
Open unit status Not open
Pre-requisites

EENG14000

Co-requisites

EENG20400

School/department Department of Electrical & Electronic Engineering
Faculty Faculty of Engineering

Description

The aim of this unit is to give students a practical introduction to digital logic design and prototyping in FPGAs based on VHDL entry, using industry standard tools. Students will work in a group of 4 to design a functioning digital system and implement it.

Intended learning outcomes

On the successful completion of this project activity students will be able to:

  1. Demonstrate, through practice, the use of VHDL as a modelling language to describe digital logic, including use of common templates to describe combinational and sequential logic blocks;
  2. Explain the hardware implications of a given piece of VHDL code and the limitations imposed in coding for synthesis;
  3. Design combinational and sequential logic blocks and finite-state machines in VHDL based on a given set of functional specifications;
  4. Interpret a specification for a digital system;
  5. Propose modular structural divisions for a complex digital system, and define interfaces for the constituent modules;
  6. Set-up and run simulations and debug VHDL code for correct functionality in the ModelSim simulator, and approach the testing and simulation of a design in a systematic manner;
  7. Use Xilinx to prototype designs in FPGAs;
  8. Prepare and give a group presentation.

Teaching details

Laboratory classes

Assessment Details

Assignment 1 (30%): An individual take-home exercise that is assessed based on functionality and quality of VHDL code, and analytical and descriptive answers, all related to design of digital circuits and systems. (ILOs 1-6)


Assignment 2(70%): A group exercise that is assessed based on the functionality and quality of submitted code to meet interim specifications (30%) and final specifications (20%). A group presentation describing the design is worth 15%. Finally, 5% of the assessment is based on the performance of the individual as viewed by their group mates and the instructors. (ILOs 1-8)

Reading and References

Two instruction booklet booklets covering principles of digital design using VHDL and the group design are provided.


The following textbooks are not required reading but provide introductory and background material to the topics covered in the Unit.


• Douglas, P., VHDL : Programming by Example, 4th Edition, McGraw-Hill 2002.
• J. Bhasker, A VHDL Synthesis Primer, 2nd ed, Star Galaxy Pub., 1998.
• M. Zwolinski, Digital System Design with VHDL, 2nd ed, Pearson Education Limited., 2004.
• P. P. Chu, RTL Hardware Design Using VHDL, John Wiley and Sons Inc., 2006.
• P. P. Chu, FPGA Prototyping by VHDL Examples, John Wiley and Sons Inc., 2006
• Wakerly, J.F., Digital Design : Principles and Practices, 4th Edition, Prentice Hall 2006.

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