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Dr Jose Nunez-Yanez


Jose Nunez-Yanez is a reader in adaptive and energy efficient computing at the University of Bristol and part of the microelectronics group. He holds a PhD in hardware-based parallel data compression from the University of Loughborough, UK with three patents awarded on the topic of high-speed parallel data compression. His main area of expertise is in the design of reconfigurable architectures for signal processing with a focus on run-time adaptation, parallelism and energy-efficiency. In 2006 he was a Marie Curie research fellow at ST Microelectronics, Milan, Italy. He investigated how to achieve an optimal coupling between a RISC processor and a dynamically reconfigurable fabric to perform automatic extensions to the standard instruction set architecture of the processor [1]. He collaborated with the European Space Agency (ESA) investigating run-time hardware adaptation to support optimal statistical compression of different data types with support by EPSRC under grant EP/D011639/1 [2]. This work was further funded by ESA through the Innovation Triangle Initiative to show the benefits of the technology in Space reducing the power and energy needs of on-board data processing systems .  He is active in the areas of power efficient computing [3] with the EPSRC ENPOWER and FP7 ENTRA projects, signal processing [4] and on-chip communication architectures [5]. In 2011 he was a royal society research fellow at ARM Ltd, Cambridge, UK investigating high-level modelling of the energy consumption of heterogeneous many-core systems [6]. This work advanced previous work that had focus on the microprocessor to add mathematical models for other components such as memory and display sub-systems. He has authored over 100 journal and conference publications.



Department of Electrical & Electronic Engineering

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