Dr José Nuñez-Yañez
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Dr Jose Luis Nunez-Yanez obtained a BSc in Industrial Engineering and a MSc in Microelectronics Engineering from the University of La Coruna (Spain) and University Politecnica the Catalunya (UPC, Spain) respectively.
Jose joined the Department of Electronic & Electrical Engineering at Loughborough University in October 1997, in order to pursue a Ph.D within the Embedded Systems Design Group. His work was focused on designing high-speed lossless data compression hardware as part of a group effort to offer innovative solutions to the high bandwidth and capacity demands generated by data-intensive applications. He investigated novel compression algorithms and architectures resulting in some of the fastest and most efficient hardware-amenable compression methods currently available. During this research, several generations of the X-MatchPRO family of lossless data compressors were developed, with each generation improving upon the previous one with higher throughputs and better compression ratios. This work was funded by EPSRC Grant GR/L54530 and GR/M86378 and it was graded as 'Outstanding'. These hardware compressors are currently some of the fastest reported to date, with throughputs up to 3.2 Gigabit/second achieved on low-cost FPGA implementations; they operate two to three times faster than commercial devices, with comparable compression levels. Four patent applications dealing with key aspects of the technology were filed.
Jose left Loughborough University in October 2004 to become a lecturer in the Department of Electronic Engineering at the University of Bristol. He has continued to work in the area of lossless data compression pioneering the use of variable order Markov models in hardware to support optimal statistical compression of multimedia data without any loss of quality and real time processing. This work is currently supported by EPSRC under grant EP/D011639/1. In addition, he is also active in other areas such as Reconfigurable Computing and high-performance embedded processors and on-chip communication architectures. During the last year Jose has been a research fellow at ST Microelectronics, Italy with a Marie Curie fellowship investigating how to achieve an optimal coupling between a RISC processor and a dynamically reconfigurable fabric to perform automatic extensions to the standard instruction set architecture of the processor with complexities ranging from sophisticated function-level instructions to simple bit manipulation extensions.
Research Interests
- Reconfigurable computing
- Lossless data compression
- Video coding
- Embedded processor architectures
- Multiprocessors
- On-chip communications
View Dr José Nuñez-Yañez's publications
Teaching Areas
- 2nd year Digital Systems
- 2nd CAD Group Project
Responsibilities
Avionics 2nd-year tutor