A low-power 6 transistor static RAM cell design which has very good static noise margin (SNM) and low power characteristics. Two additional read/write transistors are required per memory word. This design is particular suitable for robust high-density SRAMs, especially for nanoscale technology in which process variation is a major constraint. Full details and experimental results are published in IEICE Electronics Express, Vol 5, No 18, 750-755 (Singh, Pradhan et al.).
US Granted Patent 7,706,174; Priority date 15/5/2008
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