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Unit information: Advanced DSP & FPGA Implementation in 2021/22

Unit name Advanced DSP & FPGA Implementation
Unit code EENGM4120
Credit points 10
Level of study M/7
Teaching block(s) Teaching Block 2 (weeks 13 - 24)
Unit director Dr. Kris Nikov
Open unit status Not open
Pre-requisites

EENG20400 Digital Systems and knowledge of C programming

Co-requisites

None

School/department Department of Electrical & Electronic Engineering
Faculty Faculty of Engineering

Description including Unit Aims

The unit covers the topics of FPGA and DSP design as follows:

FPGA: This module extends the knowledge in digital systems with advanced topics in the emergent area of reconfigurable computing and FPGA design. The course will cover state-of-the-art features available in modern FPGAs exploring their fine-grained internal architecture and embedded macro blocks such as DSP slices and hardwired processors. A design language based on C++ will be presented as an alternative to traditional RTL design (VHDL, Verilog). High level synthesis tools will be used to map compute intensive kernels in signal processing applications from a generic DSP core to the FPGA device and the performance advantages will be evaluated.

DSP: This module extends knowledge of signal processing techniques and gives students practical experience of using the state-of-the-art DSPs. The course covers generic techniques for developing design solutions for all DSP devices as well as focussing specifically on the TMS320C6000 DSP processor which is the flagship of Texas Instruments DSPs and also the Davinci DSP processor which is a system on chip with a C6000 DSP and an Arm Processor. It also covers the use of operating systems. This module provides practical experience.

Intended Learning Outcomes

  1. Develop optimal DSP programs (Exam/Report).
  2. Implement real-time DSP algorithms for communications applications (Exam/Report).
  3. Analyse DSP device architectures and the interfacing with DSP microprocessors (Exam/Report).
  4. Describe general purpose processors and be able to compare them with Digital Signal processors (Exam/Report.
  5. List the features of modern FPGA architectures and their configuration process (Exam/Quiz).
  6. Implement hardware designs in FPGA devices (Exam/Quiz).
  7. Learn to develop C-based programs for hardware design (Exam/Assignment)
  8. Compare FPGA and DSP features and their suitability for different algorithms (Exam/Assignment).

Teaching Information

Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.

Assessment Information

DSP assignment 50% (ILOs 1,2,3,4,5, 6,7,8)

FPGA assignment 50% (ILOs 1,2,3,4,5, 6,7,8)

The unit has two parts that deal with FPGA and DSP technology and have a weight of 50% each and are taught by different academics. The DSP and FPGA components are assessed with labs completed during class and covered all the learning outcomes.

Resources

If this unit has a Resource List, you will normally find a link to it in the Blackboard area for the unit. Sometimes there will be a separate link for each weekly topic.

If you are unable to access a list through Blackboard, you can also find it via the Resource Lists homepage. Search for the list by the unit name or code (e.g. EENGM4120).

How much time the unit requires
Each credit equates to 10 hours of total student input. For example a 20 credit unit will take you 200 hours of study to complete. Your total learning time is made up of contact time, directed learning tasks, independent learning and assessment activity.

See the Faculty workload statement relating to this unit for more information.

Assessment
The Board of Examiners will consider all cases where students have failed or not completed the assessments required for credit. The Board considers each student's outcomes across all the units which contribute to each year's programme of study. If you have self-certificated your absence from an assessment, you will normally be required to complete it the next time it runs (this is usually in the next assessment period).
The Board of Examiners will take into account any extenuating circumstances and operates within the Regulations and Code of Practice for Taught Programmes.

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