| Unit name | Digital Systems |
|---|---|
| Unit code | EENG20400 |
| Credit points | 10 |
| Level of study | I/5 |
| Teaching block(s) |
Teaching Block 1 (weeks 1 - 12) |
| Unit director | Dr. Roshan Weerasekera |
| Open unit status | Not open |
| Units you must take before you take this one (pre-requisite units) | |
| Units you must take alongside this one (co-requisite units) | |
| Units you may not take alongside this one |
None |
| School/department | School of Electrical, Electronic and Mechanical Engineering |
| Faculty | Faculty of Engineering |
This unit develops topics in digital system design at an intermediate level. A further study of combinational and sequential logic focuses on issues and design methods which are relevant to modern styles of implementation, and provides a framework for later studies in VLSI design.
Views of a design: Behaviour, structure, layout.
Survey of modern technologies: VLSI, ASIC, programmable logic.
Top-down design: Classification, decomposition.
Minimisation: Definitions, minimisation of single output functions using prime implicant tables, multiple output prime implicants, variable entered Karnough maps.
MSI combinational logic blocks: Decoders, multiplexers, parity generators.
Circuit hazards: Static and dynamic hazards, logic hazards and their removal, function hazards.
Finite state machines: Moore and Mealy models, state transition graphs, ASM charts, state tables, state reduction, bubble charts, memory based state machines
Synchronous sequential circuits: state encoding, asynchronous inputs, metastability, counters and registers.
Arithmetic circuits: ripple carry adder/subtractor, carry-lookahead, carry-bypass and carry-select adders, serial and parallel multipliers, carry-save multiplication, Wallace tree, Booth algorithm.
Memory: Flash, SRAM, DRAM : read and write waveforms, SRAM/DRAM architecture, timing parameters
Programmable logic devices: FPGA architecture : look-up tables, logic cells, embedded logic blocks, CAD tools, application of FPGAs and their limitations.
Laboratory Work case study: Design and modelling of a Datapath and a controller
On successful completion of the unit a student will be able to:
Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.
Computer-based quiz on Serial Data Receiver laboratory, 15% (ILOs 3, 5)
Exam, 2 hours, 85% (ILOs 1, 2, 4-8)
If this unit has a Resource List, you will normally find a link to it in the Blackboard area for the unit. Sometimes there will be a separate link for each weekly topic.
If you are unable to access a list through Blackboard, you can also find it via the Resource Lists homepage. Search for the list by the unit name or code (e.g. EENG20400).
How much time the unit requires
Each credit equates to 10 hours of total student input. For example a 20 credit unit will take you 200 hours
of study to complete. Your total learning time is made up of contact time, directed learning tasks,
independent learning and assessment activity.
See the University Workload statement relating to this unit for more information.
Assessment
The Board of Examiners will consider all cases where students have failed or not completed the assessments required for credit.
The Board considers each student's outcomes across all the units which contribute to each year's programme of study. For appropriate assessments, if you have self-certificated your absence, you will normally be required to complete it the next time it runs (for assessments at the end of TB1 and TB2 this is usually in the next re-assessment period).
The Board of Examiners will take into account any exceptional circumstances and operates
within the Regulations and Code of Practice for Taught Programmes.
