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Unit information: Analogue Integrated Circuit Design in 2022/23

Please note: you are viewing unit and programme information for a past academic year. Please see the current academic year for up to date information.

Unit name Analogue Integrated Circuit Design
Unit code EENGM6030
Credit points 10
Level of study M/7
Teaching block(s) Teaching Block 2 (weeks 13 - 24)
Unit director Dr. Warr
Open unit status Not open
Units you must take before you take this one (pre-requisite units)

None

Units you must take alongside this one (co-requisite units)

EENGM6011

Units you may not take alongside this one
School/department School of Electrical, Electronic and Mechanical Engineering
Faculty Faculty of Engineering

Unit Information

This unit aims to equip the students with appropriate knowledge for contemporary schematic entry-driven SPICE-verified analogue integrated circuit design. The unit focuses on the use of an industry-standard toolset for IC design affording the students relevant skills for practice. Teaching is carried out in a PC laboratory with continuous practical elements and learning exercises.

The EDA package used is currently Cadence Virtuoso. The principle and application is equally applicable to all contemporary platforms offering an analogue IC design flow. The underlying algorithms of simulation and the measurement techniques are generic.

The material starts with the design flow from concept to product and then addresses in detail schematic entry, design for manufacture, circuit simulation and Process/Voltage/Temperature variation.

Students taking this unit are expected to hold an electrical/electronics-based first degree.

Your learning on this unit

On successful completion of the module, students will be able to:

  1. Describe the contemporary mechanisms for managing the engineering of an analogue IC product.
  2. List the trade-offs in analogue IC design.
  3. Discuss common-differential signal mode interpretation/operation.
  4. Apply contemporary schematic-driven design for analogue integrated circuits.
  5. Employ multiple two-port devices, characterised by their terminal characteristics, in the realisation of an analogue functionality.
  6. Analyse various analogue circuits using SPICE analysis and evaluate sub-circuit performance against a specification.
  7. Recognise the imperfect nature of integrated circuit manufacture and apply the mechanisms to accommodate, model and overcome it.
  8. Recognise high and low impedance circuit nodes and inspect associated frequency domain characteristics, assessing their implication on the overall circuit functionality.
  9. Practice designing integrated circuit amplifiers, references and feedback control systems, assess their performance and formulate alterations to the circuit to meet a specification.

How you will learn

Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.

How you will be assessed

All ILOs will be assessed via coursework.

Resources

If this unit has a Resource List, you will normally find a link to it in the Blackboard area for the unit. Sometimes there will be a separate link for each weekly topic.

If you are unable to access a list through Blackboard, you can also find it via the Resource Lists homepage. Search for the list by the unit name or code (e.g. EENGM6030).

How much time the unit requires
Each credit equates to 10 hours of total student input. For example a 20 credit unit will take you 200 hours of study to complete. Your total learning time is made up of contact time, directed learning tasks, independent learning and assessment activity.

See the Faculty workload statement relating to this unit for more information.

Assessment
The Board of Examiners will consider all cases where students have failed or not completed the assessments required for credit. The Board considers each student's outcomes across all the units which contribute to each year's programme of study. If you have self-certificated your absence from an assessment, you will normally be required to complete it the next time it runs (this is usually in the next assessment period).
The Board of Examiners will take into account any extenuating circumstances and operates within the Regulations and Code of Practice for Taught Programmes.

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