Unit information: Digital Systems in 2014/15

Unit name	Digital Systems
Unit code	EENG20400
Credit points	10
Level of study	I/5
Teaching block(s)	Teaching Block 1 (weeks 1 - 12)
Unit director	Dr. Nunez-Yanez
Open unit status	Not open
Pre-requisites	EENG14000
Co-requisites	EENG28010
School/department	School of Electrical, Electronic and Mechanical Engineering
Faculty	Faculty of Engineering

Description including Unit Aims

This unit develops topics in digital system design at an intermediate level. A further study of combinational and sequential logic focuses on issues and design methods which are relevant to modern styles of implementation, and provides a framework for later studies in VLSI design.

Elements: Digital Systems Dr J.L. Nunez-Yanez

Views of a design: Behaviour, structure, layout.

Survey of modern technologies: VLSI, ASIC, programmable logic.

Top-down design: Classification, decomposition.

Minimisation: Definitions, minimisation of single output functions using prime implicant tables, multiple output prime implicants, variable entered Karnough maps.

MSI combinational logic blocks: Decoders, multiplexers, parity generators.

Circuit hazards: Static and dynamic hazards, logic hazards and their removal, function hazards.

Finite state machines: Moore and Mealy models, state transition graphs, ASM charts, state tables, state reduction, bubble charts, memory based state machines

Synchronous sequential circuits: state encoding, asynchronous inputs, metastability, counters and registers.

Arithmetic circuits: ripple carry adder/subtractor, carry-lookahead, carry-bypass and carry-select adders, serial and parallel multipliers, carry-save multiplication, Wallace tree, Booth algorithm.

Memory: Flash, SRAM, DRAM : read and write waveforms, SRAM/DRAM architecture, timing parameters

Programmable logic devices: FPGA architecture : look-up tables, logic cells, embedded logic blocks, CAD tools, application of FPGAs and their limitations.

Laboratory Work Dr J.L. Nunez-Yanez

Case study: Design using VHDL of a serial data receiver.

Intended Learning Outcomes

On successful completion of the unit a student will be able to:

• Understand the principles of logic minimisation in combinational logic circuits and how to apply them in simple examples.

• Appreciate the range of technology available for the implementation of digital systems and be familiar with the procedure which leads to an implementation using programmable logic.

• Learn how to effectively use a hardware description language (VHDL) to design fairly complex combinatorial and sequential circuits.

• Understand the origin of hazards in combinational logic circuits, under what conditions they are problematic, and how to identify and remove them.

• Analyse and design synchronous sequential circuits using algorithmic state machine (ASM) and bubble chart design methodologies.

• Analyse the timing of synchronous circuits in waveforms, the effects of metastability and how to avoid it.

• Design efficient arithmetic circuits at the architectural level with different area/performance trade-offs.

• Understand how memory circuits work and the advantages/disadvantages of different technologies.

Teaching Information

Lectures and Laboratory classes

Assessment Information

Name: Serial Data Receiver Type: Computer-based Test % of final mark: 15 Description: On the serial Data Receiver lab assignment

Name: Terminal Exam Type: Exam % of final mark: 85 Description: 2 hour written paper

Reading and References

• Wakerley, R J.F., “Digital Design: Principles and Practices” 4th ed, Prentice Hall, 2006, ISBN 0131733494 & ISBN 8120330218

• Holdsworth, B., “Digital Logic Design” 4th ed, Butterworth-Heinemann, 2002, ISBN 0750645822

• Douglas, P., “VHDL: Programming by Example” 4th ed, McGraw-Hill, 2002, ISBN 0071400702.