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Unit information: Digital Design, Group Project in 2021/22

Unit name Digital Design, Group Project
Unit code EENG28010
Credit points 10
Level of study I/5
Teaching block(s) Teaching Block 2 (weeks 13 - 24)
Unit director Dr. Shuangyi Yan
Open unit status Not open

EENG14000, EENG20400



School/department Department of Electrical & Electronic Engineering
Faculty Faculty of Engineering

Description including Unit Aims

Unit Directors - Faezeh Arab Hassani and Shuangyi Yan

The aim of this unit is to give students a practical introduction to digital logic design and prototyping in FPGAs based on VHDL entry, using industry standard tools. Students will work in groups to design a functioning digital system and implement it.

Intended Learning Outcomes

  1. Demonstrate, through practice, the use of VHDL as a modelling language to describe digital logic, including use of common templates to describe combinational and sequential logic blocks;
  2. Explain the hardware implications of a given piece of VHDL code and the limitations imposed in coding for synthesis;
  3. Design combinational and sequential logic blocks and finite-state machines in VHDL based on a given set of functional specifications;
  4. Interpret a specification for a digital system;
  5. Propose modular structural divisions for a complex digital system, and define interfaces for the constituent modules;
  6. Set-up and run simulations and debug VHDL code for correct functionality in the ModelSim simulator, and approach the testing and simulation of a design in a systematic manner;
  7. Use Xilinx to prototype designs in FPGAs;
  8. Familiarity with good practice in design management and effective collaboration in a shared group project.

Teaching Information

Teaching will be delivered through a combination of synchronous and asynchronous sessions, including lectures, practical activities supported by drop-in sessions, problem sheets and self-directed exercises.

Assessment Information


Assignment 1 : An individual take-home exercise that is assessed based on functionality and quality of VHDL code, and analytical and descriptive answers, all related to design of digital circuits and systems. (ILOs 1-6) Marked on a Pass/Fail basis

Assignment 2 : A group exercise that is assessed based on the functionality and quality of submitted code to meet specifications (ILOs 1-8). Marked on a Pass/Fail basis


If this unit has a Resource List, you will normally find a link to it in the Blackboard area for the unit. Sometimes there will be a separate link for each weekly topic.

If you are unable to access a list through Blackboard, you can also find it via the Resource Lists homepage. Search for the list by the unit name or code (e.g. EENG28010).

How much time the unit requires
Each credit equates to 10 hours of total student input. For example a 20 credit unit will take you 200 hours of study to complete. Your total learning time is made up of contact time, directed learning tasks, independent learning and assessment activity.

See the Faculty workload statement relating to this unit for more information.

The Board of Examiners will consider all cases where students have failed or not completed the assessments required for credit. The Board considers each student's outcomes across all the units which contribute to each year's programme of study. If you have self-certificated your absence from an assessment, you will normally be required to complete it the next time it runs (this is usually in the next assessment period).
The Board of Examiners will take into account any extenuating circumstances and operates within the Regulations and Code of Practice for Taught Programmes.