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Unit information: Digital Systems in 2018/19

Please note: It is possible that the information shown for future academic years may change due to developments in the relevant academic field. Optional unit availability varies depending on both staffing and student choice.

Unit name Digital Systems
Unit code EENG20400
Credit points 10
Level of study I/5
Teaching block(s) Teaching Block 1 (weeks 1 - 12)
Unit director Dr. Nunez-Yanez
Open unit status Not open




School/department Department of Electrical & Electronic Engineering
Faculty Faculty of Engineering


This unit develops topics in digital system design at an intermediate level. A further study of combinational and sequential logic focuses on issues and design methods which are relevant to modern styles of implementation, and provides a framework for later studies in VLSI design.

Views of a design: Behaviour, structure, layout.

Survey of modern technologies: VLSI, ASIC, programmable logic.

Top-down design: Classification, decomposition.

Minimisation: Definitions, minimisation of single output functions using prime implicant tables, multiple output prime implicants, variable entered Karnough maps.

MSI combinational logic blocks: Decoders, multiplexers, parity generators.

Circuit hazards: Static and dynamic hazards, logic hazards and their removal, function hazards.

Finite state machines: Moore and Mealy models, state transition graphs, ASM charts, state tables, state reduction, bubble charts, memory based state machines

Synchronous sequential circuits: state encoding, asynchronous inputs, metastability, counters and registers.

Arithmetic circuits: ripple carry adder/subtractor, carry-lookahead, carry-bypass and carry-select adders, serial and parallel multipliers, carry-save multiplication, Wallace tree, Booth algorithm.

Memory: Flash, SRAM, DRAM : read and write waveforms, SRAM/DRAM architecture, timing parameters

Programmable logic devices: FPGA architecture : look-up tables, logic cells, embedded logic blocks, CAD tools, application of FPGAs and their limitations.

Laboratory Work case study: Design using VHDL of a serial data receiver.

Intended learning outcomes

On successful completion of the unit a student will be able to:

  1. Explain the principles of logic minimisation in combinational logic circuits and how to apply them in simple examples
  2. List the range of technology available for the implementation of digital systems and be familiar with the procedure which leads to an implementation using programmable logic
  3. Apply hardware description languages (VHDL) to design fairly complex combinatorial and sequential circuits
  4. Explain the origin of hazards in combinational logic circuits, under what conditions they are problematic, and how to identify and remove them
  5. Analyse and design synchronous sequential circuits using algorithmic state machine (ASM) and bubble chart design methodologies
  6. Analyse the timing of synchronous circuits in waveforms, the effects of metastability and how to avoid it
  7. Design efficient arithmetic circuits at the architectural level with different area/performance trade-offs
  8. Explain how memory circuits work and the advantages/disadvantages of different technologies

Teaching details

Lectures and Laboratory classes

Assessment Details

Computer-based quiz on Serial Data Receiver laboratory, 15% (ILOs 3, 5)

Exam, 2 hours, 85% (ILOs 1, 2, 4-8)

Reading and References

  • Wakerley, R J.F., “Digital Design: Principles and Practices” 4th ed, Prentice Hall, 2006, ISBN:0131733494 & ISBN:8120330218
  • Holdsworth, B., “Digital Logic Design” 4th ed, Butterworth-Heinemann, 2002, ISBN:0750645822
  • Douglas, P., “VHDL: Programming by Example” 4th ed, McGraw-Hill, 2002, ISBN:0071400702.